Mapping a real-time video algorithm to a context-switched FPGA

This paper describes the implementation of a real-time video algorithm on a context-switched FPGA. The FPGA is based on the Xilinx XC4OOOE FPGA, and includes extensions for dealing with state saving and forwarding and for increased routing demand due to time-multiplexing the hardware. The algorithm makes use of special features of this architecture to achieve high utilization of the silicon at run time. Two configuration planes are programmed as distributed RAM and two planes perform replications of the calculation in parallel. The interplay between the CLB architecture, communication between configuration planes, context-switching overhead, and the end-user application are examined as we map the algorithm onto this architecture. Background Unless an algorithm mapped to hardware can be fully pipelined, some of the hardware will be idle during the execution of the algorithm. A time-multiplexed FPGA architecture can be used to swap different parts of the algorithm into the active area of the chip. This gives us much higher utilization of the active area. The architecture is built on the work of Ong [Ong95], who first proposed rapidly reconfiguring an FPGA to increase logic capacity. A more complete description of the time-multiplexed FPGA can be found in the associated papers, [Trimberger97]. Context-Switched FPGAs The context-switched, or time-multiplexed, FPGA is an extension of the Xilinx XC4OOOE product family. We gain logic capacity by dynamically re-using hardware. SRAM bits are replicated rather than CLBs. The FPGA holds one active configuration and eight inactive configurations. The configuration memory is distributed throughout the die, with each configuration memory cell backed by eight bits of inactive storage in the configuration SRAM. This distributed inactive memory can be viewed as eight con$guration memory planes. Each plane is a very large word of memory (100,000 bits in a 20 x 20 device). When the device is&h reconjigured, all bits in the logic and interconnect array are updated simultaneously from one memory plane. This process takes about 5ns. After flash reconfiguration, about 25ns is required for signals in the design to settle. Modes of Operation A rapidly-reconfigurable FPGA is a mere curiosity without a model of use that can be used as a design target and automated. We envision three modes of operation of the device: logic engine mode, time-share mode and static mode. The video algorithm makes use of the time-share mode of operation, so we describe it here briefly. Tie Share Mode In time share (TS) mode, the FPGA emulates several independent, communicating FPGAs in a virtual hardware environment. The FPGA remains in a single contiguration for multiple user clock cycles before switching to another configuration-the reconfiguration clock is slower than the user clock rate. The FPGA may not reconfigure at fixed intervals. In time share mode, values computed in one configuration must be stored and shared with logic in other configurations. O-8186-8159-4/97 $10.00